1. Field of the Invention
The present invention relates to a circuit for controlling voltage fluctuation in an integrated circuit. The present invention relates particularly to a circuit and a method for preventing voltage fluctuation that occurs when an At Speed Test is conducted for a synchronous integrated circuit that includes an At Speed Testing mechanism.
2. Description of Background
At present, the mainstream of integrated circuits is a so-called synchronous integrated circuit (has various names such as an LSI, an LSI device, an LSI chip, a VLSI and an ASIC (Application Specific Integrated Circuit)) that includes a plurality of latches (also called flip-flops) and synchronously operates the latches in accordance with operating clock signals distributed in a tree form from a single clock source that is formed of a PLL through a plurality of clock buffers.
In order to perform functional tests for the integrated circuits at shipping, conventionally, the integrated circuits are constituted by incorporating therein additional circuits for performing tests, for example, for scan path of latches, as well as logics (logic circuits) for performing actual functions of the integrated circuits.
In this case, an external test signal is generally provided by an LSI tester, from outside the integrated circuit. But also widely employed is a BIST (Built-In Self Test) method, whereby a circuit for automatically generating a test signal is incorporated in an integrated circuit to be tested, so as to eliminate the external input of the test signal and to thereby reduce the testing cost.
It is preferable that the functional test at shipping be performed in an environment wherein the operating speed (i.e., the frequency of an operating clock signal) is the same as the original operating speed at which the integrated circuit is actually to be operated. In order to satisfy this preference, currently there has begun to be used an “At Speed Test” method, whereby the function of the logic circuit of an integrated circuit is tested by operating the integrated circuit at the actual operating speed, or at a somewhat similar speed, as that at which it normally would be operated.
An example arrangement for an integrated circuit that performs an At Speed Test is shown in prior art FIG. 1. Inside an integrated circuit 100, all latches 110, 112 and 114 are driven in synchronization with operating clock signals 108 transmitted by a PLL (Phase Locked Loop) 102, which is a clock supply source, via clock buffers 104 and 106. Data input terminals 116, 118 and 120 and latch output terminals 122, 124 and 126 of the latches 110, 112 and 114 are connected to a combinational circuit network 128 formed of logic gates, so that connections are established, via the combinational circuit network 128, between input signals 130, 132 and 134 from outside the integrated circuit 100 and the data input terminals 116, 118 and 120 of the latches, between the latch outputs 122, 124 and 126 and the data input terminals 116, 118 and 120, and between the latch output terminals 122, 124 and 126 and output signals 136, 138 and 140 to outside the integrated circuit 100.
The integrated circuit 100 is so constituted that data for the latches 110, 112 and 114 can be set not only through the normal input terminals 116, 118 and 120, but also through scan-in input terminals 142, 144 and 146. And when the latch output terminals are sequentially connected to the scan-in input terminals of different latches, as in a chain, a scan path is formed from a scan-in terminal 148 to a scan-out terminal 150, which covers all the latches of the integrated circuit 100.
With the above described arrangement, the basic At Speed Test processing includes the three following phases: (1) a scan-in phase; (2) a launch-capture phase; and (3) a scan-out phase.
Prior art FIG. 2 is a diagram showing a timing relationship after the integrated circuit 100 has been powered on and has passed through the individual phases of the At Speed Test and has begun to operate normally, and also showing the states of operating clock signals.
When a power voltage Vdd is applied to the integrated circuit 100, first, a scan-in phase 202 is started. During the scan-in phase 202, the latches 110, 112 and 114 accept input data transmitted by the scan-in input terminals 142, 144 and 146, and do not accept input data transmitted by the data input terminals 116, 118 and 120. In this phase, the shift register operation is performed using a scan clock signal (not shown) transmitted to the individual latches, i.e., data in series is set for the latches on the scan patch, beginning with the scan-in terminal 148, until finally, the initial data required to perform a functional test has been set for all the latches 110, 112 and 114 on the scan path. When the scan-in phase 202 has ended, data is no longer accepted from the scan-in input terminals 142, 144 and 146.
Sequentially, the launch-capture phase 204 is started. A signal SE 210 and a signal IR 212 are timing signals to be externally supplied by a tester for the At Speed Test. The signal SE 210 indicates that in the active state the launch-capture phase 204 has been effective, and the signal IR 212 is a pulse signal indicating the start of the launch-capture phase 204. The PLL 102 detects the entry of the At Speed Test into the launch-capture phase, and in the middle of this phase, outputs, as the operating clock signal OSC 208, several cycles (generally, two cycles) of clock pulses for the actual operating speed (the actual operating frequency). As a result, each time the clock pulses are output, the initial data that were set for the individual latches in the scan-in phase 202 are shifted to the connected latches at the succeeding stages. That is, each time the clock pulse is output, each latch captures, via several combinational gates, new data that is launched by (or released from) the preceding latch.
In the last scan-out phase 206, the shift register operation along the scan path is again rendered active, and the last data that were set for the individual latches in the launch-capture phase 204 are sequentially read, in series, from the scan-out terminal 150. The data are compared with expected value data that are prepared outside the integrated circuit 100. When the data match for all the latches, the At Speed Test is determined to have been successful, or when the data, even for one latch, do not match, the test is determined to have failed.
As described above, to perform the At Speed Test, after a specific period has elapsed following the start of the launch-capture phase 204, several cycles of clock pulses for the actual operating speed are suddenly provided for all the latches in the integrated circuit. Therefore, the values held by many latches in the integrated circuit 100 are simultaneously toggled (inverted). When such fast clock pulses are supplied to the individual latches, a large amount of current suddenly flows in and out of the integrated circuit 100. As a result, there is an increased current change (a so-called di/dt) per unit hour for all the paths in the integrated circuit 100 that supply a power voltage Vdd and a ground voltage GND, and there is a sharp fluctuation in the power voltage, especially evidenced by a voltage drop, inside the integrated circuit 100.
The problem posed by the fluctuation of the power voltage Vdd is more serious for the wire bonding part than for the input/output terminals (Area I/O) of the integrated circuit 100. For the wire bonding part, since the power voltage Vdd is supplied directly to the pads of the core chip of the integrated circuit 100 with very fine wires, the inductance value is very great. Therefore, when a large current change occurs, a large fluctuation in the power voltage Vdd also occurs.
Because of this voltage drop, the internal signal transmission speed of the integrated circuit is considerably reduced, and the internal circuits 100 may erroneously operate, with the result that some integrated circuits may not pass the At Speed Test. As described above, since the test is conducted under unrealistic and severe conditions that are not encountered during normal operation, a so-called “overkill” problem may occur and an actually “good” item determined to be a “defective” item, and the reliability and effectiveness of the At Speed Test greatly deteriorated.
In order to avoid the above described erroneous operation due to a power voltage drop that occurs during the At Speed Test, the following methods have been employed. According to one of the proposed methods, a pattern of the initial data that are set for individual latches during the scan-in phase is devised, so that the toggling of the values of the stored data occurs for only a reduced number of latches during the launch-capture phase. However, in this case, the testing period is extended, and the supply of patterns to be set for the initial data is limited. Thus, for the effectiveness of the test a problem still remains, such as the range of the test coverage.
According to another method, an integrated circuit to be tested is divided into a plurality of logic groups, and for each logic group, the At Speed Test is conducted for the logic circuits that belong to that group. In this manner, the amount of current flowing across the power voltage terminals throughout the entire integrated circuit is reduced, and consequently, a voltage drop due to a change in the current can be controlled.
For example, U.S. Pat. No. 7,007,213 discloses an invention which employs the method conducted based on division with the self test. This invention is a testing technique for an integrated circuit that includes a plurality of clock domains (i.e., logic groups), that employs the BIST (Built-In Self Test) method to perform the At Speed Test for the individual clock domains, and to detect a failure present in each clock domain and a failure present across the clock domains.
However, one of the problems of this method is that establishing a method for the division of an integrated circuit is difficult.
Furthermore, when an integrated circuit is divided into logic groups, an automatic inspection performed by operating a logic circuit for an operating clock can not actually be performed for the exchange of signals by the groups. Further, when the number of logic groups is increased, the test coverage is reduced.
In addition, a test circuit for performing such a division, and a test circuit for generating the pulse of an operating clock in a launch-capture phase at a different timing for each group, must be additionally provided. However, these circuits are complicated, and the generation and insertion of such circuits is very difficult.
The most important problem is that a test pattern, which is a pair of an initial data value to be set for each latch and an expected value for after the test, must be created using a conventional automatic test pattern generation tool (an ATPG tool), and controlling an ATPG tool is very difficult.
Consequently, it is desirable to provide a circuit that can solve the prior art problems as discussed above including the problem of voltage fluctuations which lead to reliability issues and erroneous operations of the circuit.